/**
 * Copyright (C) 2021 - 2031 O-Cubes Co., Ltd.
 */

/****************************************************************
 *  @file    dw_i2c_hal.h
 *  @brief   Designware i2c controller hal header file
 *  @version v1.0
 *  @date    03. Apr. 2023
 *  @author  liuchao
 ****************************************************************/

#ifndef __DW_I2C_HAL_H__
#define __DW_I2C_HAL_H__

#include "dw_i2c_hal_cfg.h"

/** Enable Designware I2C */
#define DW_I2C_ENABLE                   (1)
/** Disable Designware I2C */
#define DW_I2C_DISABLE                  (0)

/** Stop Condition issue after this byte */
#define IC_DATA_CMD_STOP                BIT(9)
/** Restart Condition issue after this byte */
#define IC_DATA_CMD_RESTART             BIT(10)
/** No Restart or stop condition after this byte */
#define IC_DATA_CMD_NONE                (0)

/** Perform a write request */
#define IC_DATA_CMD_WRITE_REQ           (0)
/** Perform a read request */
#define IC_DATA_CMD_READ_REQ            BIT(8)

/** Fields of IC_CON register */
/* DW_APB I2C IP Config Dependencies. */
#if DW_I2C_ALLOW_RESTART
	#define IC_CON_RESTART_EN               BIT(5)
#else
	#define IC_CON_RESTART_EN               (0x00)
#endif

/* Master Addressing Mode Config */
#if DW_I2C_MST_10_BIT_ADDR_SUPPORT
	#define MST_10_BIT_ADDR_MODE            BIT(4)
	#define IC_10BITADDR_MASTER             BIT(12)
#else
	#define MST_10_BIT_ADDR_MODE            (0x00)
	#define IC_10BITADDR_MASTER             (0x00)
#endif

/* Slave Addressing Mode Config */
#if DW_I2C_SLV_10_BIT_ADDR_SUPPORT
	#define SLV_10_BIT_ADDR_MODE            BIT(3)
#else
	#define SLV_10_BIT_ADDR_MODE            (0x00)
#endif

#if DW_I2C_SPECIAL_START_BYTE
	#define IC_TAR_SPECIAL                  BIT(11)
	#define IC_TAR_GC_OR_START              BIT(10)
#else
	#define IC_TAR_SPECIAL                  (0x00)
	#define IC_TAR_GC_OR_START              (0x00)
#endif

/** 7bit I2C address mask for target address register */
#define IC_TAR_7BIT_ADDR_MASK           (0x7F)
/** 7bit I2C address mask for slave address register */
#define IC_SAR_7BIT_ADDR_MASK           (0x7F)
/** 10bit I2C address mask for target address register */
#define IC_TAR_10BIT_ADDR_MASK          (0x3FF)
/** 10bit I2C address mask for slave address register */
#define IC_SAR_10BIT_ADDR_MASK          (0x3FF)

/** Speed modes of IC_CON */
#define IC_CON_SPEED_MASK               (0x6)
#define IC_CON_SPEED_STANDARD           (0x2)
#define IC_CON_SPEED_FAST               (0x4)
#define IC_CON_SPEED_HIGH               (0x6)
/** Working mode of IC_CON */
#define IC_CON_MST_SLV_MODE_MASK        (0x41)
#define IC_CON_ENA_MASTER_MODE          (0x41)
#define IC_CON_ENA_SLAVE_MODE           (0)

/* I2C interrupt control */
#define IC_INT_DISABLE_ALL              (0x0)
#define IC_INT_ENABLE_ALL               (0x7FF)
/* Interrupt Register Fields */
#define IC_INTR_STAT_GEN_CALL           BIT(11)
#define IC_INTR_STAT_START_DET          BIT(10)
#define IC_INTR_STAT_STOP_DET           BIT(9)
#define IC_INTR_STAT_ACTIVITY           BIT(8)
#define IC_INTR_STAT_RX_DONE            BIT(7)
#define IC_INTR_STAT_TX_ABRT            BIT(6)
#define IC_INTR_STAT_RD_REQ             BIT(5)
#define IC_INTR_STAT_TX_EMPTY           BIT(4)
#define IC_INTR_STAT_TX_OVER            BIT(3)
#define IC_INTR_STAT_RX_FULL            BIT(2)
#define IC_INTR_STAT_RX_OVER            BIT(1)
#define IC_INTR_STAT_RX_UNDER           BIT(0)

/* Interrupt enable mask as master */
#define IC_INT_MST_TX_ENABLE            (IC_INTR_STAT_TX_EMPTY | IC_INTR_STAT_TX_OVER | IC_INTR_STAT_TX_ABRT)
#define IC_INT_MST_RX_ENABLE            (IC_INTR_STAT_TX_EMPTY | IC_INTR_STAT_RX_FULL | IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER | IC_INTR_STAT_TX_ABRT)

/* Interrupt enable mask as master */
#define IC_INT_SLV_COMMON_ENABLE        (IC_INTR_STAT_START_DET | IC_INTR_STAT_STOP_DET)
#define IC_INT_SLV_TX_ENABLE            (IC_INTR_STAT_RD_REQ | IC_INTR_STAT_TX_ABRT)
#define IC_INT_SLV_RX_ENABLE            (IC_INTR_STAT_RX_FULL | IC_INTR_STAT_RX_OVER | IC_INTR_STAT_RX_UNDER)

/* IC_ENABLE_STATUS Bits */
#define IC_ENABLE_STATUS_IC_EN          BIT(0)
#define IC_ENABLE_STATUS_SLV_DIS        BIT(1)
#define IC_ENABLE_STATUS_SLV_RX_LOST    BIT(2)

/* I2C TX & RX threshold settings */
#define I2C_TX_THRESHOLD                (0)
#define I2C_RX_THRESHOLD                (0)

/* DW_APB I2C (DW_IC_STATUS) Status Register Fields. */
#define IC_STATUS_ACTIVITY              BIT(0)
#define IC_STATUS_TFNF                  BIT(1)
#define IC_STATUS_TFE                   BIT(2)
#define IC_STATUS_RFNE                  BIT(3)
#define IC_STATUS_RFF                   BIT(4)
#define IC_STATUS_MASTER_ACT            BIT(5)
#define IC_STATUS_SLAVE_ACT             BIT(6)

/* IC_TX_ABRT_SOURCE Register Bit Fields */
#define IC_TX_ABRT_7B_ADDR_NOACK        BIT(0)
#define IC_TX_ABRT_10ADDR1_NOACK        BIT(1)
#define IC_TX_ABRT_10ADDR2_NOACK        BIT(2)
#define IC_TX_ABRT_TXDATA_NOACK         BIT(3)
#define IC_TX_ABRT_GCALL_NOACK          BIT(4)
#define IC_TX_ABRT_GCALL_READ           BIT(5)
#define IC_TX_ABRT_HS_ACKDET            BIT(6)
#define IC_TX_ABRT_SBYTE_ACKDET         BIT(7)
#define IC_TX_ABRT_HS_NORSTRT           BIT(8)
#define IC_TX_ABRT_SBYTE_NORSTRT        BIT(9)
#define IC_TX_ABRT_10B_RD_NORSTRT       BIT(10)
#define IC_TX_ABRT_MASTER_DIS           BIT(11)
#define IC_TX_ABRT_ARB_LOST             BIT(12)
#define IC_TX_ABRT_SLVFLUSH_TXFIFO      BIT(13)
#define IC_TX_ABRT_SLV_ARBLOST          BIT(14)
#define IC_TX_ABRT_SLVRD_INTX           BIT(15)

/* Combined bits for i2c abort source as master */
#define I2C_MST_ABRT_ADDR_NOACK         (IC_TX_ABRT_7B_ADDR_NOACK | IC_TX_ABRT_10ADDR1_NOACK | IC_TX_ABRT_10ADDR1_NOACK)
#define I2C_MST_ABRT_LOST_BUS           (IC_TX_ABRT_ARB_LOST)
#define I2C_MST_ABRT_DATA_NOACK         (IC_TX_ABRT_TXDATA_NOACK)

/* Combined bits for i2c abort source as slave */
#define I2C_SLV_ABRT_LOST_BUS           (IC_TX_ABRT_ARB_LOST | IC_TX_ABRT_SLV_ARBLOST)

#endif /* __DW_I2C_HAL_H__ */
